Verilog HDL Example Instantiation

srffe <instance_name> (.s(<input_wire>), .r(<input_wire>),

   .clk(<input_wire>), .clrn(<input_wire>), .prn(<input_wire>),

   .ena(<input_wire>), .q(<output_wire>));

Important: To successfully perform RTL simulation and formal verification, use lowercase primitive name in instantiation.