VHDL Component Declaration
component alt_outbuf generic( io_standard : string := "NONE"; current_strength : string := "NONE"; slew_rate : integer := -1; slow_slew_rate : string := "NONE"; location : string := "NONE"; enable_bus_hold : string := "NONE"; weak_pull_up_resistor : string := "NONE"; termination : string := "NONE" ); port( i : in std_logic; o : out std_logic); end component;