Input Ports
Port Name |
Required |
Description |
Comments |
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addr[] |
Yes |
Input port used to specify which address to read, write, and/or erase. |
Input port [23..0] wide. |
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bulk_erase |
No |
Active-high input port used to erase all memory in the EPCS device. |
If asserted high, the altasmi_parallel Intel® FPGA IP performs a full erase operation that sets all memory bits of the EPCS device to1. The bulk_erase port erases the entire memory of the EPCS device, which includes the general purpose (unused) memory. |
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clkin |
Yes |
Input clock for the ASMI block. |
The maximum frequency for the clkin port is 20MHz for EPCS1 and EPCS4 devices (based on the EPCS device's maximum clock frequency). If the fast_read port is used with an EPCS16 or EPCS64 device, you can use a maximum frequency of 40 MHz for the clkin port. |
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datain[] |
No |
Input port for write and sector-protection operations. |
Input port [7..0] wide. |
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rden |
Yes |
Active-high input port used with the read port or fast_read port to continue reading the sequential addresses. |
The sequential address can be read for as long as the rden port is high. |
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read |
Yes |
Active-high input port that reads the memory address specified by the addr[] port. |
The data byte that is read appears on the dataout[] output port. If a write or erase operation is in progress (busy port is high), the read instruction is ignored. You can use both single-byte read and sequential read. You must use the read port with the rden port. Note:
The read port is disabled if the fast_read port is enabled Intel FPGA website Definition |
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fast_read |
No |
Active-high input port that reads the memory address specified by the addr[] port. |
The fast_read port allows you to use a frequency over 20 MHz on the clkin port for EPCS16 and EPCS64 devices. The data byte read that is read appears on the dataout[] output port. You can use both single-byte fast_read and sequential fast_read. If a write or erase operation is in progress (busy port is high), fast_read is ignored. Use the fast_read port with the rden input port. |
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read_sid |
No |
Active-high input port that reads the silicon ID of the EPCS device. |
The 8-bit silicon ID appears on the epcs_id output bus. Once read, the bus holds the value of the silicon ID until the device is reset. Not supported with EPCS128 devices. |
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read_status |
No |
Active-high input port that reads the EPCS status register and outputs the 8-bit binary value to the status_out[] port when asserted high. |
The read_status port can be used to determine which sectors are read-only. |
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sector_erase |
No |
Active-high input port that erases sector data. |
When asserted high, the Intel® FPGA IP performs a sector erase operation. The addr[] port indicates the sector that is erased by the sector_erase port. The address at addr[] port can be any valid address in the sector that is to be erased by the sector_erase command. |
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sector_protect |
No |
Active-high input port used that protects the memory sectors on the EPCS device. |
When asserted high, the Intel® FPGA IP takes the value of the datain[] port and writes the EPCS status register with the specified value. The tables below list the values for sector protection:
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shift_bytes |
No |
Port used to shift data bytes. |
If you use page-write mode, you must use the shift_bytes port with the write port. If this port is set to 1, the Intel® FPGA IP samples the datain[] port at the rising clkin port clock edge and as the data bytes shift through the datain[] port. This byte shifting continues until all of the bytes written into the EPCS device have been sampled and stored internally by the Intel® FPGA IP. |
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wren |
No |
Enables write and erase operations to the memory of the EPCS device. |
When wren=1, write operations and erase operations are enabled. When wren=0, write operations and erase operations are disabled. If the wren port is not used, all writes and erases are automatically enabled each time a write or erase instruction is sent to the Intel® FPGA IP. The wren port is used together with the write, sector_protect, bulk_erase, and sector_erase instruction ports. The Intel® FPGA IP checks this value before attempting to execute instructions in these instruction ports. If asserted or de-asserted by itself, no internal instructions are carried out. |
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write |
No |
Active-high input port that writes data. |
If asserted high, the Intel® FPGA IP writes from the datain[] port (single-byte write mode) or from the page-write buffer (page-write mode) to the address indicated by the addr[] port and to subsequent addresses for page-write mode. When using page-write mode, you must use the shift_bytes port to shift in data bytes before asserting the write port. |