Output Ports

busy

Yes

Output port that indicates when the altasmi_parallel Intel^® FPGA IP is performing valid instructions.

The busy port goes high when the altasmi_parallel Intel^® FPGA IP performs valid instructions. The busy port goes low when an instruction is complete.

data_valid

Yes

Output port that indicates when the dataout[] port contains a valid byte read from the EPCS memory.

The data_out[] port should be sampled when the data_valid is high.

dataout[]

Yes

Output port that holds value of the last byte read until the device is reset or new read instruction is performed.

Output port [7 DOWNTO 0] wide. The dataout[] port should be sampled when the data_valid output port is high.

epcs_id[]

No

Output port that shows EPCS silicon ID when the read_sid instruction is executed.

Output port [7 DOWNTO 0] wide. Theepcs_id[]port holds the silicon ID value until the device is reset. Theepcs_id[]port should be sampled only after thebusysignal is de-asserted.

illegal_erase

No

Output port that shows when an erase instruction has been set to a protected sector.

The illegal_erase port is required when the sector_erase or bulk_erase ports are specified. When an erase instruction is specified to a sector that is protected (through bits set in the EPCS status register), the altasmi_parallel Intel^® FPGA IP sets the illegal_erase port to high to show that a write instruction has been cancelled. The illegal_erase port pulses high for two clock periods, one clock cycle before and one clock cycle after the busy signal is pulled low and can be used to detect whether the erase instruction is performed.

illegal_write

No

Output port that shows when a write instruction has been set to a protected sector.

The illegal_write port is required when the write port is specified. When a write instruction is specified to a sector that is protected (through bits set in the EPCS status register), the altasmi_parallel Intel^® FPGA IP sets the illegal_write port to high to show when a write instruction has been cancelled. The illegal_write port pulses high for two clock periods and one clock cycle before and one clock cycle after the busy signal is pulled low and can be used to detect whether the write instruction is performed.

read_address[]

No

Output port that shows which address the data byte is read from.

Output port [23 DOWNTO 0] wide. Theread_address[]port must be used with thedataout[]port.

rdid_out[]

No

Output port that shows memory capacity.

Output port [7 DOWNTO 0] wide. Therdid_out[]port holds a memory capacity value after a read_rid instruction. Therdid_out[]port should be sampled only after thebusysignal is de-asserted.

status_out[]

No

Output port that shows the contents of the EPCS 8-bit status register.

Output port [7 DOWNTO 0]wide.Thestatus_out[]port holds the status register value until a newread_statusinstruction is performed. To obtain the most recent status register contents, you must perform a read_status instruction before sampling thestatus_out[]port. Otherwise, thestatus_out[]port may hold an old or invalid value. You should sample thestatus_out[]port only after thebusysignal is de-asserted.