RES-50005: RAM Control Signals Driven by Flip-Flops with Asynchronous Clears

Description

Detected flip-flops driving RAM control signals (address/Read Enable/Write Enable) with asynchronous clear signals. Flip-flops with Asynchronous Clear signals drive control signals which can result in RAM corruption due to a RAM internal timing violation.

Recommendation

Remove the asynchronous clear signal if a circuit naturally resets when reset is held long enough to reach steady-state equivalent of a full reset.

Severity

Low

Device Family