Domains Tab (View Menu) (Platform Designer)
The Domains tab displays a
list of all the Avalon®-MM domains in the system,
allowing you to specify interconnect parameters. When you select a domain in the Domains tab, the corresponding selection highlights in the
System View tab.
Click
to display this tab.You open this tab in Platform Designer by clicking .
- Filter the System View tab to display a single Avalon® domain, or multiple domains. Further filter your view with selections in the Filters dialog box.
- To rename an Avalon® memory-mapped domain, double-click the domain name. Detailed information for the current selection appears in the Avalon® domain details pane.
- On the Domain tab, specify interconnect parameters.
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To enable and disable the highlighting of the Avalon® domains in the tab, click the domain control tool at the bottom of the tab.
Option | Description | ||||||
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Specifies the maximum number of pipeline stages that Platform Designer can insert in each command and response path to increase the fMAX at the expense of additional latency. You can specify between 0 and 4 pipeline stages, where 0 means that the interconnect has a combinational datapath. This setting is specific for each Platform Designer system or subsystem. |
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Clock crossing adapter type |
Specifies the default implementation for automatically
inserted clock crossing adapters:
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Automate default slave insertion | Directs Platform Designer to automatically insert a default slave for undefined memory region accesses during system generation. | ||||||
Enable instrumentation | When you set this option to TRUE, Platform Designer enables debug instrumentation in the Platform Designer interconnect, which then monitors interconnect performance in the system console. | ||||||
Interconnect reset source | Select Default or a specific reset signal in your design. | ||||||
Burst adapter implementation |
Allows you to choose the converter type that Platform Designer applies to each burst.
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Width adapter implementation |
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Enable ECC protection |
Specifies the default implementation for ECC protection
for memory elements.
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Interconnect type |
Allows you to select the implementation of Platform Designer interconnect. You can select one of
the following options:
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Use synchronous reset | When set to True, all registers in the interconnect use synchronous reset. Assert the reset for at least 16 cycles and start transactions 16 cycles after deassertion of the reset. This period allows all the IP components to reset and come out of the reset state. To avoid deadlocks in the interconnect, reset masters and slaves simultaneously. If masters and slaves have different resets, reset slaves only after responding to all necessary transactions. The Use synchronous reset option is enabled by default for Intel® Stratix® 10 designs, but is disabled by default for all other designs. Enabling synchronous reset for the interconnect does not enable synchronous reset for IP components in the system. You must separately enable the synchronous reset parameter for any component. |