Snapshot Viewer Commands

You can access these commands by clicking the Snapshot Viewer icon in the Compilation Dashboard. You can run the Snapshot Viewer to assist with timing closure and design analysis after running the Plan, Place, or Route stages of the Fitter. The Snapshot Viewer allows you to run various analysis tasks from the Flow Navigator to achieve faster timing closure and maximize design performance.

Table 1. Snapshot Viewer Tasks and Commands
Design Task	Available at Snapshot	Snapshot Viewer Commands
Timing Closure—Analyze Failing Paths	Planned, Placed, Routed	List Top Failing Paths—lists all top failing paths in Snapshot Selections. Select a path to locate in RTL Viewer or Chip Planner. Show Full Timing Path in the Schematic—highlights the path in RTL Viewer for further analysis. Show Full Timing Path in the Chip View—highlights the path in Chip Planner for further analysis. View Path Characteristics—The path loads in the Timing Analyzer for further analysis.
Timing Closure—Analyze Clocking	Placed	Show Global Clock Visualization—loads the Global Signal Visualization report for the snapshot that allows you to visualize clock sector utilization.
Timing Closure—Analyze High Fanout Nets	Placed, Routed	List High Fanout Nets—lists high fan-out nets in Snapshot Selections. Select a path to locate in RTL Viewer or Chip Planner. Show High Fanout Nets in the Schematic—highlights the paths in RTL Viewer for further analysis. Show High Fanout Nets in the Chip View—highlights the paths in Chip Planner for further analysis.
Timing Closure—Validate Constraints	Planned, Placed	Timing Exceptions— the Tcl Console reports analysis of the project .sdc file.
Timing Closure—Analyze Congestion	Placed, Routed	Show Logic Lock Regions with Congestion Heat Map—the Chip Planner displays the Logic Lock regions in a congestion heat map for further analysis.