Partial Reconfiguration Page (Device and Pin Options Dialog Box)

Allows you to specify options for partially reconfuring a portion of a target FPGA, which the remaining portions of the FPGA continue to function. You can specify these option:

• Enable Partial Reconfiguration pins—enables the PR_REQUEST, PR_READY, PR_ERROR, PR_DONE, DCLK, and DATA[15..0] pins. Partial reconfiguration (PR) with an external host or external scrubbing requires these pins. An external host uses the PR_REQUEST pin to request partial reconfiguration or external scrubbing, the PR_READY pin to determine if the device is ready to receive programming data, the PR_ERROR pin to externally monitor programming errors, and the PR_DONE pin to indicate the device finished programming. If this option is turned off, these pins are not available as PR pins when the device operates in user mode and the dual-purpose programming pins are available as user I/O pins. Not available for Intel^® Stratix^® 10 devices.
• Enable open drain on Partial Reconfiguration pins—enables open drain on the PR_READY, PR_ERROR, and PR_DONE Partial Reconfiguration pins. Not available for Intel^® Stratix^® 10 devices.
• Generate Partial-Masked SOF files (.pmsf)—generates .pmsf file containing both configuration data and region definitions that can be used to re-configure a device region. If this option is turned on, the .pmsfgenerates instead of Mask Settings files (.msf).
• Generate Partial Reconfiguration Raw Binary File (.rbf)—Generates a Partial Reconfiguration Raw Binary File (.rbf) containing configuration data that an intelligent external controller can use to reconfigure the portion of target device.