Partition Statistics Report

All Device Families Except Arria^® V, Cyclone^® V , and Stratix^® V

Summarizes partition merge statistics for each defined partition in your design. The Statistics column displays resources including logic utilization, clock control blocks, adaptive lookup tables (ALUTs) usage, logic registers, DSP Blocks, registers, adaptive logic module (Adaptive Logic Module (ALM) Definition) utilization, logic array block (Logic Array Block (LAB) Definition) utilization, multiplier block Definition, I/O pins, virtual pins Definition, connections, partition interface, congestion, port connectivity and registered ports.

Each partition column displays the results of calculations for that particular resource as either an integer count of resources used in the design, or as a fraction; resources used/total resources available.

Arria^® V, Cyclone^® V , and Stratix^® V Device Families

The Fitter Partition Statistics report forArria^® V , Cyclone^® V , and Stratix^® V device families displays a detailed analysis of logic utilization based on calculations of ALM usage.

Logic utilization is the metric for how many ALMs are needed to implement the design, displayed as a fraction of the total ALMs available on the target device, or, ALMs needed / total ALMs on the device. The report displays logic utilization as the result of operations on the number of ALMs fulfilling different functions.

ALMs needed—lists the results of the following calculation:

ALMs used in final placement – ALMs recoverable by dense packing + ALMs unavailable

• ALMs used in final placement—Calculated as the sum of the following factors:

  • ALMs used for LUT logic and registers—Lists the number of ALMs that implement both look-up table (LUT) logic functions and registers. ALMs are fracturable, that is, the Fitter configures the ALM for a variety of uses; for example, a 1-input LUT driving a FF, two 6-input LUTs in shared-LUT mode driving two registers.
  • ALMs used for LUT logic—Lists the number of ALMs that implement only LUT logic.
  • ALMs used for registers—Lists the number of ALMs that are used by passing a signal through to the register without invoking a logical operation.
  • ALMs used for memory (up to 1/2 of total ALMs)—Lists the number of ALMs that used to implement memory bits in core logic. These ALMs operate in LUTRAM mode, and are grouped together in Memory LABs (MLAB Definition).
• ALMs recoverable by dense packing - estimated—An estimate of the number ALMs which can be recovered as the design grows. This metric estimates the amount of recoverable logic in units of ALMs. During Place and Route optimization, the Intel^® Quartus^® Prime software permits logic to use more area than is required, improving optimization metrics such as Fmax. However, as the design grows and more logic is added, you may need to know what amount of that space can be recovered. For example, the Intel^® Quartus^® Prime software may be able to recover ALMs by packing unrelated LUTs and registers together into the same ALMmore aggressively, but this aggressive packing my reduce the Fmax performance of your design.
• Estimate of ALMs unavailable—An estimate of ALMsthe number of ALMs in LABs that are not used, and are unlikely to be usable, due to various design and device constraints. ALMs combine to form LABs and each LAB contains ten ALMs. After your design undergoes Place & Route, some LABs typically contain unused ALMs, however, not all unused ALMs can be targeted. Specific reasons for unusable ALMs include constrained logic, signal conflicts, LAB input limits and virtual I/Os. The Estimate of ALMs unavailable metric is the sum of the following factors:
  • Due to location constrained logic—The number of ALMs where only part of the ALM is used. If you specify the location of a logic element in the top or bottom part of the ALM, no other unlocked logic elements are combined with that element in the top or bottom part of the ALM.
  • Due to LAB-wide signal conflicts—The number of control signals that drive elements in each LAB which are restricted, such as clock, sload, and sclr. If the populated ALMs in a LAB use most of the control signals, it is unlikely that other logic could be added to the LAB.
  • Due to LAB input limits—The number of signals that can arrive into each LAB is restricted. If the populated ALMs in a LAB use most of the LAB inputs, it is unlikely that other logic could be added to the LAB.
  • Due to virtual I/Os—When you specify virtual I/Os, the Intel^® Quartus^® Prime software implements them as LUTs, then packs and places them to allocate the space they potentially occupy. However, they don't count as used, nor can they be packed with non-virtual core logic.

Difficulty packing design—This estimate is based on the types of packing algorithms required in order to fit your design using the number of LABs on the targeted device. The clustering phase of the Fitter attempts increasingly more aggressive packing strategies, until all logic can be fit or a no-fit due to clustering is declared. The packing algorithms consists of four categories; Low, Medium, High, and No-Fit. High packing difficulty may indicate that fitting the design into the target device required Fmax performance trade-offs.

Total LABs: partially or completely used—The number of LABs which contain ALMs implementing the design. LABs can be fully used, with all ALMs implementing logic, or partially used, with as little as a single ALM implementing logic. This metric distinguishes between Logic LABS and Memory LABs, which can be up to ½ of the total LABs.

Combinational ALUT usage for logic—Core user logic in a design is synthesized into look-up tables (Combinational ALUTs) of one to seven inputs. Combinational ALUT usage is a count of the total number of such functions in the design, and it is a purely logical count. The exact amount of ALM hardware required to implement the logic is unknown prior to fitting. A rough estimate of the amount of ALM hardware needed for implementing LUT functions can be computed by assuming that all six-input functions will use a full ALM (though it may not be the case for the particular design in question), and that all smaller input functions will be successfully packed into the same ALM (although a small percentage of such functions may not be successfully paired, and each will be using its own ALM). For example, in a design with 20,000 Combinational ALUT functions of up to 5-inputs, and 10,000 Combinational ALUT functions of 6 and 7-input functions, the total combinational ALUT count is 30,000, but the number of ALMs used to implement the design can range from 15000 to 30000. Note that these are theoretical limits and are unlikely. It is necessary to run the fitter to obtain an accurate utilization in terms of ALMs.

Combinational ALUTs used for route-throughs—These are LUT resources that are used for the purpose of driving a signal into a register that is not driven directly by a LUT packed in the same ALM.

In an ALM, the Fitter can choose from multiple paths to drive a register's data input signal. There are dedicated paths, sometimes referred to as a "sneak paths", that bypass the LUT logic; and there are direct paths, sometimes referred to as"route throughs", that drive through the LUT logic. In certain situations, it may be faster to drive the register via a route through if the LUT is otherwise unused for other logic. If the Fitter uses a route through, overall logic utilization is not reduced because the LUT was unavailable to pack a real logic function.

This metric is not part of the logical count of Combinational ALUTs in the design, since it is an implementation detail.

Dedicated logic registers—Displays the total number of logic registers in the design, to be implemented with core logic (ALMs). The exact amount of ALM hardware required to implement the register logic is unknown prior to fitting. The Dedicated logic registers metric displays the usage of registers By type and By function.

• ·By type—Displays the calculation of Primary logic registers and Secondary logic registers as fractions; logic registers used/total logic registers.
• ·By function—Displays the calculation of logic registers used as implementation registers and routing optimization registers.
  Note: Arria^® V , Cyclone^® V , and Stratix^® V device family ALMs contain four registers; the two registers from previous architecture are reported in the Primary logic registers row, and the two additional registers are reported in the Secondary logic registers row. The secondary registers are used internally for timing closure optimization via register duplication. On particular designs, the secondary registers can be used for implementing user logic registers.