Timing-Driven Synthesis logic option
A logic option that specifies whether Analysis & Synthesis should use the design's SDC timing constraints to better optimize the circuit. When this option is turned on, Analysis & Synthesis runs timing analysis to obtain timing information about the netlist, and then takes into account the SDC timing constraints to only focus on critical portions of the design when optimizing for performance, while optimizing non-critical portions for area. When you turn on this option Analysis & Synthesis also protects SDC constraints by not merging duplicate registers that have incompatible timing constraints.
Turning on this option causes Analysis & Synthesis to increase performance by improving logic depth on critical portions of the design and to improve area on non-critical portions of the design. The increased performance comes at the cost of area, specifically ALUTs and registers in the design. Depending on how much of the design is timing critical, overall area may increase or decrease when the Timing-Driven Synthesis option is tuned on. Runtime and peak memory use will increase slightly as well.
Turning on the Timing-Driven Synthesis logic option affects the manner in which the Optimization Technique logic option is applied, as described in the following table:
|
Optimization Technique Logic Option Setting |
Behavior of the Timing-Driven Synthesis Logic Option |
|---|---|
|
Speed |
Timing-critical parts of the circuit are optimized for speed, but logic usage is increased minimally over of the amount of logic used when the Timing-Driven Synthesis logic option is turned off, which may result in slightly worse timing but better logic utilization. |
|
Balanced |
Timing-critical parts of the circuit are optimized for speed, and logic usage is limited to resources available on the device. |
|
Area |
Logic usage does not increase; however, timing-driven synthesis prevents duplicate registers with incompatible timing-constraints from merging independent of the Optimization Technique option setting. |
This option is useful when Analysis & Synthesis does not optimize the circuit well for the given timing constraints or if too great of an area increase occurs when the Optimization Technique logic option is set to Speed.
This option is ignored if the Synthesis Effort logic option is set to Fast.
This option is available for supported device (Arria® series, Cyclone® III, Cyclone® IV, Stratix® III, Stratix® IV, and Stratix® V) families.
| Scripting Information |
|
Keyword: synth_timing_driven_synthesis Devices: Arria® II, Cyclone® III, Cyclone® IV, Stratix® III, Stratix® IV, and Stratix® V Settings: on | off |