Match PLL Compensation Clock logic option
This logic option allows you to specify a PLL output clock feeding a clock network as a compensation target for a PLL in NORMAL or SOURCE_SYNCHRONOUS mode. This option configures the PLL to match its feedback path to the target's clock network.
This option is ignored if it is assigned to anything other than a PLL output clock.
This option is available for the Stratix® V device family only.
Scripting Information |
Keyword: match_pll_compensation_clock |