Logic Cell Insertion logic option

A logic option assignment that allows you to insert one or more logic cells between two nodes without changing the design files. The value that you assign to this option is the number of logic cells you want to insert. The inserted logic cell(s) act as a simple buffer and do not alter the functionality of the design. This option is useful for increasing the delay on a data path by inserting logic cell buffers to correct clock hold and for relieving routing congestion.

If you use this logic option as a single point assignment, the logic cell(s) are inserted after the assigned node. The output of the assigned node then drives the newly inserted logic cell(s), and the logic cell(s) drive the fan-outs of the node.

If you use this logic option as a point-to-point assignment between a source and destination node, the logic cell(s) are inserted between the source node and the destination node it feeds. The source node then feeds the newly inserted logic cell(s), and the logic cells feed the destination node.

The Compiler ignores this assignment if it is assigned to anything other than a node. This option is available for supported device (MAX^® II, and MAX^® V) families.