Verilog HDL Example Instantiation

alt_iobuf my_iobuf (.i(internal_sig1), .oe(enable_sig),
   .o(internal_sig2), .io(bidir)); //bidir must be declared as an inout pin
defparam my_iobuf.io_standard = "3.3-V PCI";
defparam my_iobuf.current_strength = "minimum current";
defparam my_iobuf.slow_slew_rate = "on";
defparam my_iobuf.location = "iobank_1";
defparam my_iobuf.enable_bus_hold = "on";
defparam my_iobuf.weak_pull_up_resistor = "off";
defparam my_iobuf.termination = "series 50 ohms";