Input Ports

clock

No

Clock port for the lpm_clshift Intel^® FPGA IP.

Required if the value of the LPM_PIPELINE parameter is greater than zero.

aclr

No

Asynchronous clear.

When the aclr port is asserted the function is asynchronously reset.

clken

No

Clock enable.

When the clk_en port is asserted, a shift operation takes place. Otherwise no operation occurs and the outputs remain unchanged.

data[]

Yes

Data to be shifted.

Input port LPM_WIDTH wide.

distance[]

Yes

Number of positions to shift data[] in the direction specified by the direction port.

Input port LPM_WIDTHDIST wide.

direction

No

Direction of shift. Low = left (toward the MSB), high = right (toward the LSB).

Default value is 0 (low) = left (toward the MSB).