VHDL Component Declaration
Note: The VHDL Component Declaration
for the csfifo Intel® FPGA IP does not include the threshlevel[], threshold, or
usedw[] ports because these signals are not
supported in Intel® Quartus® Prime VHDL.
COMPONENT csfifo GENERIC (LPM_WIDTH : POSITIVE; LPM_NUMWORDS : POSITIVE); PORT (data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0); wreq, rreq, clock, clockx2, clr : IN STD_LOGIC; empty, full : OUT STD_LOGIC; q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)); END COMPONENT;