TMC-20001: Timing Paths With Impossible Hold Requirement
Description
Timing paths with a very large negative hold requirement complicate timing closure and can cause excessively long run times. These paths are not valid and require appropriate timing constraints, such as:
- set_clock_groups to avoid invalid clock domain crossing paths
- set_false_path for invalid timing path
- set_multicycle_path to adjust clock edges of a multi-cycle setup path.
Note: The hold_requirement_threshold_level rule parameter filters out hold paths with more stringent timing requirements (that is, a smaller slack value). Specify a negative value for this parameter that is a specific fraction (for example, 50%) of the design's clock period to multiple clock cycles.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| slack_threshold | A violation is reported for timing paths that have slack more negative than the value of this parameter. | double | -5.0 | 0.0 |
Recommendation
Ensure that the timing path is valid. Otherwise, apply an appropriate timing exception ( set_false_path or set_multicycle_path ) or restructure the path.
Severity
High
Device Family
- Intel® Agilex™
- Intel® Stratix® 10
- Intel® Arria® 10
- Intel® Cyclone® 10 GX