RES-50005: RAM Control Signals Driven by Flops with Asynchronous Clears
Description
RAM control signals (address/Read Enable/Write Enable) were driven by flops with asynchronous clear signals.
Recommendation
Remove asynchronous clear if a circuit naturally resets when reset is held long enough to reach steady-state equivalent of a full reset.
Severity
Low
Device Family
- Intel® Agilex™
- Intel® Stratix® 10