AND Primitive
|
Names: |
Output Description: |
Input Description: |
|---|---|---|
|
AND2, AND3, AND4, AND6, AND8, AND12 |
OUT = logical AND of inputs |
IN1, IN2, ...IN12= 2, 3, 4, 6, 8, or 12 inputs |
Note: In Verilog HDL, you must use the built-in and gate primitive to
implement the AND logic function. Go to Using a Verilog HDL Gate
Primitive for more information.