Hierarchy tab

Displays, by default, the top-level design entity of the current project. After analysis and elaboration, compilation, or simulation, click the + icon to expand a top-level design entity and view the names of any sub-entities of the top-level entity.

Columns in the Hierarchy tab list resources used by the design entity (including the design entity) and the number of resources (in parentheses) instantiated by the design entity at that level in the hierarchy.

Post-synthesis values are displayed after synthesis, and post-fitting values are displayed after fitting in resource usage columns for each partition. Entity types displayed include logic cells, RAM, DSP elements, I/O registers, adaptive logic modules (ALMs), look up tables (LUTs), and adaptive lookup tables (ALUTs).