TMC-20010: Logic Level Depth

Description

Large logic level depth restricts the clock speed at which the circuit can operate.

Note: Use the Logic_Level_Threshold parameter to modify the threshold value for deep logic level depth paths.

Parameter

Name Default Value Description
Logic_Level_Threshold 5

Reports a violation for paths that have logic levels more than specified in this parameter.

Recommendation

Restructure the design by adding pipeline registers to remove performance bottlenecks and increase achievable clock frequency for the design.

Severity

Medium

Stage

Plan, Place, Finalize

Device Family

  • Intel® Stratix® 10
  • Intel® Agilex™
  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10