TMC-20001: Timing Paths With Impossible Hold Requirement
Description
Timing paths with a very large negative hold requirement complicate timing closure and can cause excessively long run times. These paths are not valid and need appropriate timing constraints, such as:
- set_clock_groups to avoid invalid clock domain crossing paths
- set_false_path for invalid timing path
- set_multicycle_path to adjust clock edges of a multi-cycle setup path.
Note: The hold_requirement_threshold_level rule parameter filters out hold
paths with more stringent timing requirements (that is, a smaller slack value).
Specify a negative value for this parameter that is a specific fraction (for
example, 50%) of the design's clock period to multiple clock cycles.
Parameter
| Name | Default Value | Description |
|---|---|---|
| hold_requirement_threshold_level | -0.5 nS |
Reports a violation for timing paths that have hold time requirement more stringent than the value specified for this parameter. |
Recommendation
Ensure that the timing path is valid. Otherwise, apply an appropriate exception (set_false_path or set_multicycle_path) or restructure the path.
Severity
High
Stage
Plan
Device Family
- Intel® Stratix® 10
- Intel® Agilex™
- Intel® Cyclone® 10 GX
- Intel® Arria® 10