RES-50004: Multiple Asynchronous Resets within Reset Synchronizer Chain
Description
All of the registers in a reset synchronizer chain must be reset by the same signal source. Otherwise, the chain does not properly synchronize the reset signal feeding the head of the chain. This condition can cause glitches and inconsistencies in downstream data signals.
Recommendation
Ensure that there is a common source that feeds the asynchronous reset pin of every register in the same reset synchronizer chain.
Severity
High
Stage
Plan, Place, Route, Final
Device Family
- Intel® Agilex™
- Intel® Stratix® 10
- Intel® Cyclone® 10 GX
- Intel® Arria® 10