RES-50003: Asynchronous Reset Missing Timing Constraint
Description
The release of asynchronous reset signals must not only be followed by a reset synchronizer chain, but must also be constrained in a way that prevents the Timing Analyzer from analyzing asynchronous reset signals as timed, synchronous transfers. Static timing analysis cannot accurately analyze such paths.
Design Assistant can identify a reset transfer as asynchronous under any of the following conditions:
- The reset signal is from an unconstrained input
- The clock domain of the reset signal is unrelated/asynchronous to the latching domain of the register being reset
Recommendation
When a reset transfer is intended to be asynchronous, either constrain it with a set_false_path or set_clock_groups -asynchronous constraint, or relax the timing on the transfer by constraining it with a set_max_delay constraint whose value is greater than the latch clock's period.
Severity
High
Stage
Plan, Place, Route, Final
Device Family
- Intel® Agilex™
- Intel® Stratix® 10
- Intel® Cyclone® 10 GX
- Intel® Arria® 10