RES-30131: Reset Nets with Polarity Conflict

Description

This rule verifies whether a driver drives the SCLR (or CLRN) ports of multiple registers with opposite polarities. This condition can be common if you connect the wrong reset polarity to a block of logic, or code the wrong polarity in you RTL.

When the reset is released and most of the logic is toggling, the registers with the wrong polarity are held in reset. In addition, these registers in simulation and hardware appear to be "stuck-at 0 or 1".

Note: Intel® Quartus® Prime Pro Edition synthesis can synthesize regular datapath logic to use the SCLR port of a register. In that case, Design Assistant may indicate a rule violation, even though no actual logic reset is present. Confirm that the driver is actually a system reset, or if either of the signals are coded with the wrong reset polarity. If not, you can ignore the rule violation.
Figure 1. Example Register Driving SCLR Ports of two Flip-Flops with Opposite Polarities. The following example shows a register ff_feeding_slcr that drives SCLR ports of two flip-flops, ff_with_sclr_0 and ff_with_sclr_0, with opposite polarities:
Figure 2. Example Input Pin Driving CLRN ports of four Flip-Flops with CLRN Ports with Opposite Polarity. The following example shows a areset~ input pin that drives CLRN ports of four flip-flops, where CLRN ports of ff_with_aclr_0[1:0] have opposite polarity with CLRN ports of ff_with_aclr_1[1:0]:

Recommendation

Verify the intended polarity of the reset nets, and modify the RTL to unify the reset polarity.

Severity

Medium

Stage

Synthesis

Device Family

  • Intel® Stratix® 10
  • Intel® Agilex™
  • Intel® Arria® 10