PDI-20100: Platform Designer Interconnect Timing Violation
Description
The design contains failing timing path between Platform Designer interconnect components.
Recommendation
Add pipeline stages between <componentA> and <componentB> by following these steps in Platform Designer:
- Open the Platform Designer system that has this violation.
- In the right-hand pane, go to Domains tab and click on Show System with Interconnect button, which launches the System with Platform Designer Interconnect window.
- In the System with Platform Designer Interconnect window, go to Memory-Mapped Interconnect tab.
- In the Interconnect drop-down menu, select the interconnect that has the failing path (for example, mm_interconnect_N in the following image).
- Select the Show Pipelinable Locations check box. This results in displaying all pipelinable locations.
- Identify components A and B in the interconnect, right-click on their gray boxes and select Pipelined.
Severity
Medium
Stage
Finalize
Device Family
- Intel® Stratix® 10
- Intel® Agilex™