CLK-30002: Clock Source Driving Non-clock Pins
This generic rule aims at catching clocking issues that are not reported by more specific clock structures, such as:
- multiplexed clocks
- clock dividers that are not based on synchronous counters or state-machines
- D-latches based on the asynchronous load feature
When a design contains clock signal sources that connect to ports other than clock ports, the design is considered asynchronous (having associated issues and challenges of asynchronous designs).
The following image shows an example of a clock signal source that incorrectly drives the input pin of an AND gate:
Recommendation
Clock signal source in a design should drive only clock input ports of registers. Correct the connectivity, if it was not intended.
Severity
High
Stage
Analysis and Elaboration
Device Family
- Intel® Cyclone® 10 GX
- Intel® Arria® 10