CDC-50003: CE-Type CDC Missing Skew Constraints
When a multi-bit data transfer to a DFFE (D Flip-Flop with Enable)
register crosses asynchronous clock domains, and the enable signal to the DFFE is
synchronous with the latching domain, you must constrain the skew of the bits on the
data bus. Otherwise, there is no guarantee that all bits of the bus latch on the same
clock cycle.
Recommendation
Apply a set_max_skew constraint to each bit of a DFFE bus to ensure that all bits latch on the same clock cycle.
In the following example, the enable signal is synchronized, but requires a max skew constraint on the n-bit data transfer:
Severity
High
Stage
Plan, Place, Route, Finalize
Device Family
- Intel® Stratix® 10
- Intel® Agilex™
- Intel® Cyclone® 10 GX
- Intel® Arria® 10