CDC-50001: 1-Bit Asynchronous Transfer Not Synchronized

Description

Single-bit asynchronous data transfers must be followed by a synchronizer chain. A synchronizer chain is a linear sequence of registers in the same clock domain. Otherwise, the transfer may experience metastability.

A data transfer is considered asynchronous if its launch and latch clocks are unrelated or asynchronous. Clocks are unrelated if they do not share a common parent clock. Clocks are asynchronous if they are explicitly designated as such via a clock group or clock-to-clock false path. Data transfers are also asynchronous if their destination register has the Synchronizer Identification = FORCED instance assignment.

Recommendation

Ensure that single-bit asynchronous data transfers are protected by a synchronizer chain. To do this, add one or more synchronizer registers after the destination of the transfer, with each register in the same clock domain as the destination of the transfer, and with no fan-out between them.

To confirm whether the chain is long enough to prevent metastability, run the report_metastability command in the Timing Analyzer.

If you do not intend a violating transfer to be asynchronous, ensure that the launch clock of the transfer is correct and is related to the latch clock of the transfer.

Figure 1. Unsynchronized 1-bit Asynchronous Transfer. To prevent a CDC-50001 violation, the blue register in the following figure must be followed by at least one other register also latched by clkb.

Severity

High

Stage

Plan, Place, Route, Finalize

Device Family

  • Intel® Stratix® 10
  • Intel® Agilex™
  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10