CLK-30030: PLL Setting Violation

Design Assistant detected inconsistent settings between a clock assigned to a PLL and the settings for the PLL.

Recommendation

Verify that all clocks that are assigned to a PLL have settings consistent with the PLL settings. Design Assistant reports inconsistent settings and an unmatched number of clocks. Modify the clock assignment to match PLL settings.

Severity

High

Stage

Final

Device Family

• Intel^® Arria^® 10
• Intel^® Cyclone^® 10 GX