To perform a gate-level functional simulation of a VHDL design with the IES GUI
- If you have not already done so, set up the Incisive Enterprise Simulator working environment.
- To start the IES software, type nclaunch at a command prompt.
- On the File menu, click Set Design Directory.
- Browse to your design directory.
- Click Create cds.lib File. In the New cds.lib File dialog box, select the libraries to include and click Save.
- Under Work Library,
click New.Note: Intel recommends using the IES (Verilog or (VHDL) default library names when you create a library. You should name the IES software libraries as follows:
- When you run the IES software independently from the Intel® Quartus® Prime software, you should name your library work.
- When you run the IES software automatically from the Intel® Quartus® Prime software to perform a gate-level simulation, your library is automatically named gate_work under the current project directory, and the work alias is mapped to the gate_work directory.
- Specify your new work library name; for example, type work.
- Click OK.
- Repeat steps 7 and 8 for each functional simulation library; for example, for other work library names, you could type lpm, altera_mf, altera.
- In the Set Design Directory dialog box, click OK.
- If not already done, on the Edit menu, click Setup File Types, and add *.vo and *.svo as NCVlog file types, and *.vho as the NCVhdl file type.
- In the Library Browser, right-click the files you want to compile, and then click NCVhdlon the pop-up menu.
- In the Compile VHDL dialog box, you will see a list of all of the files you selected. Apply any wanted options, and then click OK.