useioff VHDL Synthesis Attribute
A VHDL synthesis attribute that directs the Intel® Quartus® Prime software to implement input, output, and output enable registers in I/O cells that have fast, direct connections to an I/O pin, when possible. Using this option can improve I/O cell performance by minimizing setup, clock-to-output, and clock-to-output enable times.
To use the useioff synthesis attribute, first declare the synthesis attribute with a boolean type using an Attribute Declaration. Then use an Attribute Specification to associate the useioff synthesis attribute with a Port Declaration of a top-level VHDL entity. Specifying the useioff synthesis attribute as true directs the Intel® Quartus® Prime software to pack registers into the I/O cells representing the port. Specifying the useioff synthesis attribute as false prevents register packing into the I/O cells. If you associate the synthesis attribute with any other VHDL object, or if you specify an illegal (non-Boolean) value, the synthesis attribute is ignored.
For example, in the following code, the Attribute Declaration declares the useioff synthesis attribute, and the Attribute Specifications direct the Intel® Quartus® Prime software to implement the registers a_reg, b_reg, and o_reg in the I/O cells corresponding to the ports a, b, and o, respectively:
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity top_level is port ( clk : in std_logic; a, b : in unsigned(1 downto 0); o : out unsigned(1 downto 0)); attribute useioff : boolean; attribute useioff of a : signal is true; attribute useioff of b : signal is true; attribute useioff of o : signal is true; end top_level; architecture rtl of top_level is signal o_reg, a_reg, b_reg : unsigned(1 downto 0); begin -- rtl process(clk) begin a_reg <= a; b_reg <= b; o_reg <= a_reg + b_reg; end process; o <= o_reg; end rtl;