direct_enable VHDL Synthesis Attribute
A VHDL synthesis attribute that directs Intel® Quartus® Prime Integrated Synthesis to which signals to use as clock enable signals to the registers. Using this attribute prevents Intel® Quartus® Prime Integrated Synthesis from synthesizing a different clock enable from the one that you prefer to use.
Analysis & Synthesis also recognizes the synonymous synthesis attribute syn_direct_enable. This synthesis attribute behaves identically to the direct_enable synthesis attribute.
In the example code below, Intel® Quartus® Prime Integrated Synthesis would normally create a clock enable equation for the registers that would include both signals ce0 and ce1. However, with the direct_enable attribute set to ce1, ce1 is the clock enable signal and ce0 is part of the logic feeding the data input of the registers.
library ieee; use ieee.std_logic_1164.all; entity top is port ( d : in std_logic_vector(31 downto 0); clock, ce0, ce1 : in std_logic; q : out std_logic_vector(31 downto 0) ); end top; library altera; use altera.altera_syn_attributes.all; architecture rtl of top is attribute direct_enable of ce1 : signal is true; begin -- rtl process(clock) begin if(rising_edge(clock)) then if(ce1 = '1') then if(ce0 = '1') then q <= d; end if; end if; end if; end process; end rtl;
You can also use this attribute to prevent Intel® Quartus® Prime Integrated Synthesis from "unmapping" a clock enable signal, that is, synthesizing the clock enable signal back into the data input of the register. Intel® Quartus® Prime Integrated Synthesis sometimes unmaps clock enable signals that qualify as underutilized. If you want a specific signal to be the clock enable signal, setting this attribute prevents Intel® Quartus® Prime Integrated Synthesis from unmapping the clock enable signal.