SGR-30021: More Than One Asynchronous Port of a Register Driven by the Same Signal Source
To avoid race conditions in your design, avoid using the same signal source to drive more than one asynchronous port on a register. The following ports are affected:
- aload
- adata
- preset
- clear
Recommendation
Restructure the netlist to avoid multiple asynchronous ports of a register being driven by the same signal.
Severity
High
Stage
Analysis and Elaboration
Device Family
- Intel® Arria® 10
- Intel® Cyclone® 10 GX