RES-50004: Multiple Asynchronous Resets within Reset Synchronizer Chain

All of the registers in a reset synchronizer chain must be reset by the same signal source. Otherwise, the chain does not properly synchronize the reset signal feeding the head of the chain. This condition can cause glitches and inconsistencies in downstream data signals.

Recommendation

Ensure that there is a common source that feeds the asynchronous reset pin of every register in the same reset synchronizer chain.

The following examples show multiple asynchronous resets within a reset chain that triggers Design Assistant violation RES-50004.

Figure 1. Multiple Asynchronous Resets Driving Many Registers in a Reset Chain
Figure 2. Sub-Optimal Asynchronous Resets Driving Many Registers in a Reset Chain

Severity

High

Stage

Plan, Place, Route, Final

Device Family

  • Intel® Agilex™
  • Intel® Stratix® 10
  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10