NSS-30012: Design Contains Latches

Latches are structures where two sets of two-input combinational logic (which the compiler implements in logic cells) are cross-coupled using combinational loops. These combinational loops drive the output of one set of logic to an input of the other set of logic.

Note: Often, latches are observed due to RTL coding error. This rule helps in catching those RTL errors.

A latch can cause glitches and ambiguous timing in a design, which makes timing analysis of the design difficult. In addition, a latch can cause significant stability and reliability problems in a design. This is because the behavior of the combinational loops in the latch often depends on the relative propagation delays of the combinational loop's logic, causing the combinational loop to behave differently under different operation conditions.

Following image illustrates an example SR-latch:

Figure 1. SR-Latch

Following image shows an example of D-latch based on an SR latch:

Figure 2. D-Latch Based on an SR Latch

Recommendation

Do not include latches in your design.

Severity

High

Stage

Analysis and Elaboration

Device Family

  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX