CDC-50002: 1-Bit Asynchronous Transfer Missing Timing Constraint

Ensure that a synchronizer chain follows a single-bit asynchronous data transfer. Also, constrain such transfers to prevent the Timing Analyzer from analyzing the transfers as timed, synchronous transfers. Such paths cannot be accurately analyzed by static timing analysis.

A data transfer is considered asynchronous if its launch and latch clocks are unrelated or asynchronous. Clocks are unrelated if they do not share a common parent clock. Clocks are asynchronous if they are explicitly designated as such via a clock group or clock-to-clock false path. Data transfers are also asynchronous if their destination register has the Synchronizer Identification = FORCED instance assignment.

Recommendation

If you intend for the transfer to be asynchronous, either apply the set_false_path or set_clock_groups -asynchronous constraint, or relax the timing on the transfer with a set_max_delay constraint whose value is greater than the latch clock's period.

If a violating transfer was not intended to be asynchronous, ensure that the launch clock of the transfer is correct and is related to the latch clock of the transfer.

To prevent a CDC-50002 violation, there must be either a false path, asynchronous clock group, or relaxing max delay on the transfer from the orange register to the leftmost blue register in the following figure:

Figure 1. Synchronized 1-bit Asynchronous Transfer

Severity

High

Stage

Plan, Place, Routed, Finalize

Device Family

  • Intel® Stratix® 10
  • Intel® Agilex™
  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10