Derive Clock Uncertainty (derive_clock_uncertainty)

You access the functions of this dialog box by clicking Timing Analyzer's Constraints > Derive Clock Uncertainty, or with the derive_clock_uncertainty Synopsys^® Design Constraints (SDC) command.

Directs the Timing Analyzer to use the derive_clock_uncertainty command to calculate and apply setup and hold clock uncertainties for clock-to-clock transfers found in the design.

Note: You should update your timing netlist after running the Derive Clock Uncertainty command.

Add clock uncertainty assignment:

Turn on the Add clock uncertainty assignment option to add clock uncertainty values from assignments created with the Set Clock Uncertainty command to uncertainty values derived by the Derive Clock Uncertainty command.

Overwrite existing clock uncertainty assignments:

Turn on the Overwrite existing clock uncertainty assignments option to overwrite user-defined clock uncertainty assignments created with the Set Clock Uncertainty command.

SDC Command:

Displays SDC commands for the options you specify in this dialog box.