ID:13510 Verilog HDL conditional expression warning at <location>: expression is wider than one bit
CAUSE: In a Verilog Design File (.v), you used a multi-bit expression in a condition expression. Quartus Prime Integrated Synthesis will reductively OR the bits in the expression together to form the conditional signal.
ACTION: If you intended to use a multi-bit expression in a condition expression, then no action is required. Otherwise, revise the expression so that it evaluates to a single bit.