To perform a gate-levelfunctional simulation with the QuestaSim GUI
- If you have not already done so, set up a project with the QuestaSim software.
- To map the design libraries to
your work library:
- On the File menu, point to New and click Library. The Create a New Library dialog box appears.
- Type lpm in the Library Name box, type the name of the work library in the Library Maps to box, and then click OK.
- Repeat steps 2a and 2b to map altera_mf to the work library.
- To compile the functional
simulation libraries, Verilog HDL or VHDL Design
Files, and testbench files (if you are using a
testbench):
- To load the design:
- On the Simulate menu, click Simulate. The Simulate dialog box appears.
- In the Name list, click the + icon to expand the work directory.
- Select the top-level design file to simulate.
- Click Add.
- Click Load.
- Perform the functional simulation in the QuestaSim software.