EDA Formal Verification Hierarchy logic option

A logic option that determines how to process the hierarchy of design entities during formal verification. The option applies only to the design entity to which it is assigned; lower-level entities do not inherit their parent entity's setting for this option.

The option is useful during formal verification. The EDA Formal Verification Hierarchy option does not tell the Intel^® Quartus^® Prime software to preserve hierarchy during compilation. The EDA Formal Verification Hierarchy option affects the formal verification script generated by the Intel^® Quartus^® Prime software by marking entities as black-boxes in the formal verification script. The EDA Formal Verification Hierarchy option also changes the Verilog Output File (.vo) Definition by treating the entity as a black box.

This option must be assigned to a design entity. This option is available for all Intel devices.