Using Verilog HDL in the Intel® Quartus® Prime Software
Specifying Verilog HDL Input Settings
Inserting an HDL Template
Implementing Combinational Logic
Implementing Sequential Logic
- Implementing Registers
- Implementing Counters
- Implementing Latches
- Implementing State Machines
Creating Hierarchical Projects
- Using a Intel® Quartus® Prime Logic Function
- Using a Verilog HDL Gate Primitive
- Implementing a User-Defined Intel® FPGA IP or Macrofunction
- Using Parameterized Functions
- Implementing RAM & ROM
- Implementing Inferred RAM
Note: For more information about using Verilog HDL in the Intel® Quartus® Prime software, see the
"Intel® Quartus® Prime Integrated Synthesis" chapter in the Intel® Quartus® Prime Handbook,
vol. 1.