altera_attribute Verilog HDL Synthesis Attribute
A Verilog HDL or SystemVerilog synthesis attribute for making assignments in theIntel® Quartus® Prime software to objects in your HDL source files. You can use it to embed assignments in your source files when the assignments do not have a specific synthesis attributes. The attribute takes a single string value with the same syntax as an assignment in a Tcl script or the Intel Quartus Prime Settings File (.qsf) Definition. The Intel® Quartus® Prime software only supports altera_attribute on modules, instances, ports, and inferred registers. If applied to any other object, the synthesis attribute is ignored.
Assignments made with the altera_attribute synthesis attribute are not displayed in the Assignment Editor or written to the Intel® Quartus® Prime Settings File. Assignments made with the altera_attribute synthesis attribute are listed in the Source Assignments report in the Analysis & Synthesis folder of the Compilation Report.
<declaration> (*altera_attribute = "\ -name<name_1><value_1> [-to<target_1> ] [-from<source_1> ] [-section_idsection_1 ];\ -name<name_2> <value_2>[-to<target_2> ] [-from<source_2> ] [-section_idsection_2 ];\ [...]" *)
In this code:
- <name_1> and <name_2> are the names of QSF variables.
- <value_1> and <value_2> are the QSF variables' corresponding values.
- <target_1> and <target_2> are optional tags which specify the target instances this assignment should apply to within this entity.
- <source_1> and <source_2> are optional tags which specify the source instances that this assignment should apply to within this entity.
- <section_1> and <section_2> are optional tags which specify the sections that this assignment should apply to.
Not all assignment types would need a target, a source or a section. If a QSF variable requires a string value, use escaped quotes around the value, as shown in the following example, which uses a non-existent variable and value:
(* altera_attribute = "-name VARIABLE_NAME \"STRING_VALUE\"" *) reg q;
(* altera_attribute = "-name POWER_UP_LEVEL HIGH" *) reg q;
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *) module foo(a, b, c, o);
The following example shows how you can also use altera_attribute for more complex assignments involving more than one instance. In this example, the following Verilog HDL statements use an altera_attribute to cut all timing paths from q1 to q2:
reg q2; // Equivalent to set_instance_assignment -name CUT ON -from q1 -to q2 (* altera_attribute = "-name CUT ON -to q2" *) reg q1;
You may specify either the -to option or the -from option in a single altera_attribute; integrated synthesis automatically sets the remaining option to the target of the altera_attribute. You may also specify wildcard characters Definition for either option. For example, if you specify * for the -to option instead of q2, the Intel® Quartus® Prime software cuts all timing paths from q1 to every other register in the design.