Performing a Functional Simulation with the VCS Software
To prepare for a functional simulation of a Verilog HDL design with the Synopsys® VCS software, you can type a command that compiles the design and generates a simv.exe file that you can use to simulate the design. Alternatively, you can type a command that compiles and simulates the design automatically.
To perform a functional simulation of a Verilog HDL design with the VCS software from the command line:
Note: For more information about using EDA simulators, refer to
Synopsys®
VCS and VCS MX Support in the Intel® Quartus® Prime Handbook.