A pulse generator in a design should not generate pulses in any of the
following ways:
Creating a wide glitch using a two-input AND, NAND, OR, or NOR gate, where the source for
the two gate inputs are the same, but the design inverts the source for one of the
gate inputs.Figure 1. Asynchronous Pulse Generator Example
Using a register where the register output drives the register's own
asynchronous reset signal through a delay chain (one or more consecutive nodes that
act as a buffer for creating intentional delay).Figure 2. Asynchronous Pulse Generator Example
These pulse generators are asynchronous, where the generated pulse width
can never be reliably predefined. As a result, the pulse width depends on the circuit
delay. For example, the pulse width generated by a pulse generator that uses a 2-input
AND gate depends on the relative delays of the path
that drives the AND gate directly and the path that the
design inverts before driving the AND gate.
Recommendation
A pulse generator should generate pulses as shown in the following example image of a
recommended pulse generator that is implemented in a synchronous manner: