CDC-50002: 1-Bit Synchronized Missing Constraint

This 1-bit transfer between unrelated clock domains is synchronized, but there is no constraint on the transfer to distinguish it from a timed transfer.

Recommendation

Either designate this transfer as asynchronous with the set_false_paths or set_clock_groups -asynchronous constraint, or relax the timing on this path with the set_max_skew constraint and a set_max_delay constraint with a value greater than the destination clock period.

Severity

High

Stage

Finalize

Device Family

  • Intel® Stratix® 10
  • Intel® Agilex™
  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10