ACD-30025: Data Bits Are Not Correctly Synchronized When Transferred Between Asynchronous Clock Domains

This rule applies when data bits across asynchronous clock domains are synchronized, but fail to adhere to the synchronization guidelines of triggering two or more cascading synchronization registers by the same clock edge.

The following image shows an example of the incorrect transfer of all data bits between asynchronous clock domains. When the cascaded synchronization registers are triggered on different clock edges, the risk is higher that the second register does have enough time to resolve the metastable output from the first register.

Figure 1. Incorrect Transfer of all Data Bits Between Asynchronous Clock Domains Example

The following image shows an example of the incorrect transfer of all data bits between asynchronous clock domains. The logic is inserted between the output of the transmitting clock domain and the cascaded synchronization registers in the receiving asynchronous clock domain. The synchronizer may sample unintended data due to glitches generated by the combinational logic. In addition, the extra toggling on the output of the combinatorial logic also increases the risk of metastability.

Figure 2. Incorrect Transfer of all Data Bits Between Asynchronous Clock Domains Example

Recommendation

Synchronize data bits as recommended in the following:

  • Trigger the cascading register synchronization on the same clock edge.
  • Do not insert any logic between the output of the transmitting clock domain and the cascaded register synchronization in the receiving asynchronous clock domain.

Severity

High

Stage

Analysis and Elaboration

Device Family

  • Intel® Arria® 10
  • Intel® Cyclone® 10