RES-30010: Reset Signal That is Generated in One Clock Domain and Used in Another Clock Domain is Not Synchronized

In a design, a reset signal that is generated in one clock domain and used in one or more other asynchronous clock domains must be synchronized. A reset signal that is not synchronized can cause metastability problems.

The following image shows an example of a reset signal that is generated in one clock domain and used in one or more other asynchronous clock domains that is not synchronized:

Figure 1. A Reset Signal That is not Synchronized

Recommendation

Follow these guidelines for synchronization of the reset signal:

  • Synchronize the reset signal with two or more cascading registers in the receiving asynchronous clock domain.
  • Trigger the cascading registers on the same clock edge.
  • Do not include any logic between the output of the transmitting clock domain and the cascaded registers in the receiving asynchronous clock domain.

The following image shows an example of a synchronized reset signal:

Figure 2. Synchronized Reset Signal

Important: Synchronizing the reset signal delays the signal by an extra clock cycle. This delay should be considered when using the reset signal in a design.

Severity

Medium

Stage

Analysis and Elaboration

Device Family

  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10