RES-30009: Reset Signal That is Generated in One Clock Domain and Used in Another Clock Domain is Incorrectly Synchronized

This rule applies when asynchronous clock domain signals are synchronized but fails to adhere to synchronization guidelines of two or more cascading synchronization registers triggered by same the clock edge.
The asynchronous clock domain synchronization using single register is not considered complete as it leaves probability of metastability in the receiving domain. Hence, you require two cascading registers to decrease the probability of metastability in the receiving domain.

The following image shows an example of an incorrectly synchronized reset signal.

Figure 1. Incorrectly Synchronized Reset Signal

Similarly, when cascading synchronization registers are triggered on different clock edges, the risk is higher that the second register does not have enough time to resolve the metastable output from the first register. Hence, the cascading registers should be triggered on same clock edges. The following image shows an example of an incorrectly synchronized reset signal:

Figure 2. Incorrectly Synchronized Reset Signal

Also, any additional logic should not exist between the output of the transmitting clock domain and cascading registers in the receiving asynchronous clock domain. This is because the extra toggling on the output of the combinatorial logic increases the risk of metastability resulting in synchronizer sampling unintended data (due to the glitches generated by the combinational logic). The following image shows an example of an incorrectly synchronized reset signal.

Figure 3. Incorrectly Synchronized Reset Signal

Recommendation

Follow these guidelines for a reset signal that is generated in one clock domain and used in one or more other asynchronous clock domains:

  • Synchronize the reset signal with two or more cascading registers in the receiving asynchronous clock domain.
  • Trigger the cascading registers on the same clock edge.
  • Do not include any logic between the output of the transmitting clock domain and the cascading registers in the receiving asynchronous clock domain.

The following image shows an example of a correctly synchronized reset signal:

Figure 4. Correctly Synchronized Reset Signal

Important: Synchronizing the reset signal delays the signal by an extra clock cycle. This delay should be considered when using the reset signal in a design.

Severity

High

Stage

Analysis and Elaboration

Device Family

  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10