NSS-30015: Multiple Pulses Generated in the Design

A design should not contain structures that generate multiple pulses in the following ways:

  • Each structure contains a 2-input AND, NAND, OR, or NOR gate.
  • The AND or OR gate output drives one of the gate's own inputs through an inverted delay chain (one or more consecutive nodes that act as a buffer for creating intentional delay). Alternatively, the NAND or NOR gate output drives one of the gate's own inputs through a delay chain.
  • A triggering signal drives the gate's other input.

The following image shows an example of multiple pulses:

Figure 1. Multiple Pulses

Recommendation

Do not include structures that generate multiple pulses in your design. These structures generate widths for multiple pulses that are difficult for the Intel® Quartus® Prime Pro Edition software to determine, set, or verify. For example, the pulse widths are difficult for the Intel® Quartus® Prime software to determine if Analysis and Synthesis and the Fitter have not already determined the node delays necessary for the pulse widths.

Structures that generate multiple pulses cause more problems than pulse generators because of the number of pulses involved. In addition, when the structures generate multiples pulses, they also increase the frequency of the design.

Severity

High

Stage

Analysis and Elaboration

Device Family

  • Intel® Arria® 10
  • Intel® Cyclone® 10