PLL Bandwidth logic option

This logic option allows you to specify the PLL bandwidth preset setting. PLL bandwidth is the measure of the PLL"™s ability to track the reference clock and its associated jitter. Bandwidth is approximately the unity gain point for open loop PLL response. The bandwidth setting allows you to control the bandwidth over a finite range to customize the PLL characteristics for a particular application. The Intel^® Quartus^® Prime software provides four bandwidth settings — low, medium, high, and auto. The auto setting directs the Intel^® Quartus^® Primesoftware to select the default setting based on the reference clock and PLL output clock frequency.

A high-bandwidth PLL provides a fast lock time and tracks jitter on the reference clock source, passing it through to the PLL output. A low-bandwidth PLL filters out reference clock jitter, but increases lock time. For example, the programmable bandwidth feature in Stratix^® V PLLs benefits different types of systems requiring clock switchover.

A high-bandwidth PLL can benefit a system that must accept a spread-spectrum clock signal. PLLs can track a spread-spectrum clock by using a high-bandwidth setting. Using a low-bandwidth setting in this case could cause the PLL to filter out the jitter on the input clock.

A low-bandwidth PLL can benefit a system using clock switchover. When clock switchover occurs, the PLL input temporarily stops. A low-bandwidth PLL reacts more slowly to changes on its input clock and takes longer to drift to a lower frequency (caused by the input stopping) than a high-bandwidth PLL.

This option is available for the Stratix^® V device family only.